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tm fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer october 2006 ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 fin24c serdes?low-voltage 24-bit bi-directional serializer/deserializer features low power for minimum impact on battery life ? multiple power-down modes ? ac coupling with dc balance 100na in standby mode, 5ma typical operating conditions cable reduction: 25:4 or greater bi-directional operation 50:7 reduction or greater up to 24 bits in either direction up to 20mhz parallel interface operation voltage translation from 1.65v to 3.6v ultra-small and cost-effective packaging high esd protection: >7.5kv hbm parallel i/o power supply (v ddp ) range between 1.65v to 3.6v applications micro-controller or pixel interfaces image sensors small displays ? lcd, cell phone, digital camera, portable gaming, printer, pda, vid eo camera, automotive general description the fin24c serdes? is a low-power serializer/ deserializer (serdes) that can help minimize the cost and power of transferring wide signal paths. through the use of serialization, the nu mber of signals transferred from one point to another can be significantly reduced. typical reduction is 4:1 to 6:1 for unidirectional paths. for bi-directional operation, using half duplex for multiple sources, it is possible to increase the signal reduction to close to 10:1. through the use of differential signaling, shielding and emi filters can also be minimized, further reducing the cost of serialization. the differential signal- ing is also important for providing a noise-insensitive sig- nal that can withstand radio and electrical noise sources. major reduction in power consumption allows minimal impact on battery life in ul tra-portable applications. a unique word boundary technique assures that the actual word boundary is identified when the data is deserial- ized. this guarantees that each word is correctly aligned at the deserializer on a word-by-word basis through a unique sequence of clock and data that is not repeated except at the word boundary. a single pll is adequate for most applications, including bi-directional operation. ordering information pb-free package per jedec j-std-020b. bga and mlp packages available in tape and reel only. serdes tm is a trademark of fairchild semiconductor corporation. order number package number pb-free package description fin24cgfx bga042 yes 42-ba ll ultra small scale ball grid array (uss-bga), jedec mo-195, 3.5mm wide FIN24CMLX mlp040 yes 40-terminal molded leadless package (mlp), quad, jedec mo-220, 6mm square
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 2 functional block diagram figure 1. block diagram ckref cks0+ cksi+ + ? + ? + ? + ? cksi- cksint cksint oe oe dso+/dsi- serializer control word ck generator freq. control direction control power down control control logic 0 i word boundary generator serializer deserializer deserializer control pll i/o control note: m = 20 or 22 register register register dso-/dsi+ 100 gated termination 100 termination diro cks0- ckp s1 s2 diri strobe dp[m+1:24] dp[1:m]
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 3 terminal description note: 1. the dso/dsi serial port terminals have been arranged such that when one device is rotated 180 to the other device, the serial connections properly align without the need for any traces or cable signals to cross. other layout orientations may require that traces or cables cross. terminal name i/o type number of terminals description of signals dp[1:20] i/o 20 lvcmos parallel i/o, direction controlled by diri terminal dp[21:24] i or o 4 lvcmos parallel unidirectional inputs or outputs dependent on state of s1, s2 terminals ckref in 1 lvcmos clock input and pll reference strobe in 1 lvcmos strobe signal for latching data into the serializer ckp out 1 lvcmos word clock output dso+ / dsi? dso? / dsi+ diff-i/o 2 ctl differential serial i/o data signals(1) dso: refers to output signal pair dsi: refers to input signal pair dso(i)+: positive signal of dso(i) pair dso(i)?: negative signal of dso(i) pair cksi+, cksi? diff-in 2 ctl differential deserializer input bit clock cksi: refers to signal pair cksi+: positive signal of cksi pair cksi?: negative signal of cksi pair ckso+, ckso? diff-out 2 ctl differential serializer output bit clock ckso: refers to signal pair ckso+: positive signal of ckso pair ckso?: negative signal of ckso pair s1 in 1 lvcmos mode selection pins used to define mode of operation for some terminals. the control terminals, dp[21:24] can be set as 4 terminals in the same direction or two in each direction. s2 in 1 diri in 1 lvcmos control input used to control direction of data flow diro out 1 lvcmos control output inversion of diri v ddp supply 1 power supply for parallel i/o and translation circuitry v dds supply 1 power supply for core circuitry and serial i/o v dda supply 1 power supply for analog pll circuitry gnd supply 0 use bottom ground plane for ground signals
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 4 connection diagrams figure 2. terminal assignments for mlp (top view) figure 3. terminal assignments for bga 1 2 3 4 5 6 7 8 9 10 dp[9] dp[10] dp[11] dp[12] v ddp ckp dp[13] dp[14] dp[15] dp[16] 30 29 28 27 26 25 24 23 22 21 diro ckso+ cdso- dso+ / dsi- dso- / dsi+ cksi- cksi+ diri s2 v dds 11 12 13 14 15 16 17 18 19 20 dp[17] dp[18] dp[19] dp[20] dp[21] dp[22] dp[23] dp[24] s1 v dda 40 39 38 37 36 35 34 33 32 31 dp[8] dp[7] dp[6] dp[5] dp[4] dp[3] dp[2] dp[1] strobe ckref (top view) 1 2 3 4 5 6 a b c d e f j pin assignments 1234 5 6 a dp[9] dp[7] dp[5] dp[3] dp[1] ckref b dp[11] dp[10] dp[6] dp[2] strobe diro c ckp dp[12] dp[8] dp[4] ckso+ ckso- d dp[13] dp[14] v ddp gnd dso- / dsi+ dso+ / dsi- e dp[15] dp[16] gnd v dds cksi+ cksi- f dp[17] dp[18] dp[21] v dda s2 diri j dp[19] dp[20] dp[22] dp[23] dp[24] s1
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 5 control logic circuitry the fin24c has four signals that are selectable as two unidirectional inputs and two uni directional outputs, or as four unidirectional inputs or four unidirectional outputs. these are often used by applications for control signals. the mode signals s1 and s2 determine the direction of the dp[21:24] data si gnals. the 00 state provides for a power-down state where all functionality of the device is disabled or reset. the diri terminal controls the direc- tion of the device in modes 1 and 3. when in mode 2, the direction is controlled by bo th the diri and strobe sig- nals. table 1 provides a complete description of the vari- ous modes of operation. for unidirectional operation, the diri terminal should be hardwired to a valid logic level and the diro terminal should be left floating. for bi- directional operation, the diro of the master device should be connected to the diri of the slave device. when operating in a bi-directional mode, the turn-around functionality is dependent on t he mode of the device. for modes 1 and 3, the device asynchronously passes and inverts the diri signal through the device to the diro signal. care must be taken during design to ensure that no contention occurs between the deserializer outputs and the other devices on this port. optimally the periph- eral device driving the serializer should be in a high- impedance state prior to the diri signal being asserted. when a device with dedicated data outputs turns from a deserializer to a serializer, the dedicated outputs remain at the last logical value asserted. this value only changes if the device is once again turned around into a deserializer and the values are overwritten. when the device is in mode 2 (s2 = 1, s1 = 0), the direc- tion of operation is de pendent upon both the strobe signal and the diri signal. at power-up, the mode select signals are both low and the diro signal is the inver- sion of the diri signal. after power-up, the diri and strobe signal should initially both be high. when strobe goes low the device is configured as a serial- izer and diro will be forced low. the device remains a serializer until the diri signal goes low. when diri goes low, the device is re-configured as a deserializer and the diro signal is asserted high. when operating the serdes in pairs, not all operating modes are compatible. regardless of the mode of oper- ation, the serializer is always sending 24 bits of data and two word boundary bits. the deserializer is always receiving 24 bits of data and two word boundary bits. for some modes of operation, not all of the data bits are valid because some pins are dedicated inputs or outputs. a value of ?0? is sent in the serial stream for all invalid data bits. table 1. control logic circuitry mode number inputs output device state description s2 s1 strobe diri diro 0 0 0 x 0 1 na power-down state. the device is powered down and disabled regardless of all other signals. x10 na 1 0 1 x 0 1 des 4-bit unidirectional control mode dp[21:24] are outputs x10 ser 2 1 0 0 0 1 des 4-bit unidirectional control mode dp[21:24] are inputs strobe and diri operate as an rs-latch to change the state of operation. in general, diri and strobe should not be low at the same time. 01 0 ser 10 1 des 1 1 diro (n-1) previous 3 1 1 x 0 1 des 2-bit unidirectional control mode dp[21:22] are inputs dp[23:24] outputs 1 1 x 1 0 ser 2-bit unidirectional control mode dp[21:22] are inputs dp[23:24] outputs
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 6 4-bit control mode when operating in 4-bit control mode, the master device must be configured as mode 2 (s2 = 1, s1 = 0) and the slave device must be config ured as mode 1 (s2 = 0, s1 = 1). when operating in this mode, 24 data and control bits can be sent from the master to the slave and 20 data bits can be sent from the sl ave to the master. unidirec- tional control signals should be connected to dp[21:24]. 2-bit control mode when operating in 2-bit control mode, both devices must be configured in mode 3 (s2 = s1 = ?1?). in this mode, 22 bits can be sent in either direction. when operating in a 2-bit control mode, serialized bits 21 and 22 appear on outputs 23 and 24 of the deserializer. power-down mode: (mode 0) mode 0 is used for powering down and resetting the device. when both of the mode signals are driven to a low state, the pll and refere nces are disabled, differ- ential input buffers are shut off, differential output buffers are placed into a high-impedance state, lvcmos out- puts are placed into a high-impedance state, lvcmos inputs are driven to a valid level internally, and all inter- nal circuitry is reset. the loss of ckref state is also enabled to ensure that the pll only powers up if there is a valid ckref signal. in a typical application, t he device only changes between the power-down mode and t he selected mode of opera- tion. this allows for system-l evel power-down functional- ity to be implemented via a single wire for a serdes pair. the s1 and s2 selection signals that have their operat- ing mode driven to a ?logic 0? should be hardwired to gnd. the s1 and s2 signals that have their operating mode driven to a ?logic 1? should be connected to a system level power-down signal.
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 7 serializer operation mode the serializer configuration is described in the following sect ions. the basic serialization circuitry works essentially the same in these modes, but the actual data and clock stre ams differ depending on if ckref is the same as the strobe signal or not. when ckref equals strobe, t he ckref and strobe signals are hardwired together as one signal. when ckref does not equal strobe, each signal is distinct and ckref mu st be running at a frequency high enough to avoid any loss of data condition. ckref must never be a lower frequency than strobe. the phase-locked loop (pll) must receive a stable ckref signal to achieve lock prior to any valid data being sent. the ckref signal can be used as the data strobe signal, provided that data can be ignored during the pll lock phase. once the pll is stable and locked, the device can begin to capture and serialize data. data is captured on the rising edge of the strobe signal and then serial- ized. the serialized data stream is sy nchronized and sent source synchronously with a bit clock with an embedded word boundary. serialized data is sent at 26 times the ckref clock rate. two additional data bits are sent that define the word boundary. when in this mode, the internal deserializer circuitry is disabled; includ- ing the serial clock, serial data input buffers, the bidirectional parallel outputs, and the ckp word clock. the ckp word clock is driven high. figure 4. serializer timing diagram (ckref equals strobe) if the same signal is not used for ckref and strobe, the ckref signal must be run at a higher frequency than the stro be rate to serialize the data correctly. the actual serial transfer rate remains at 26 times the ckref frequency. a data bit value of zero is sent when no valid data is present in the serial bit stream. the operation of the serializer otherwise remains the same. the exact frequency that the reference clock needs is dependent upon the stabil- ity of the ckref and strobe signal. if the source of the ckref signal imple- ments spread spectrum technology, the maximum frequency of this spread spectrum clock should be used in calculating the ratio of strobe frequency to the ckref frequency. similarly if the strobe signal has significant cycle-to- cycle variation, the maximum cycle-to-cycle time needs to be factored into the selection of the ckref frequency. figure 5. serializer timing diagram (ckref does not equal strobe) word n-1 word n-2 word n-1 word n dpi[1:24] ckref dso cks0 b 24 b 25 b 26 b 1 b 2 b 3 b 4 b 1 b 2 b 3 b 4 b 5 b 22 b 23 b 24 b 25 b 26 word n+1 word n word n-1 word n-1 word n no data no data ckref dp[1:24] dso cks0 strobe b 1 b 2 b 3 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 22 b 23 b 24 b 25 b 26 word n+1 word n serializer operation: (figure 4) diri = 1, ckref = strobe serializer operation: (figure 5), diri = 1, ckref does not = strobe
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 8 serializer operation mode (continued) a third method of serialization can be accomplished with a free running bit clock on the cksi signal. this mode is enabled by grounding the ckref signal and driving the diri signal high. at power-up, the device is configured to accept a serialization clock from cksi. if a ckref is received, the device enabl es the ckref serialization mode. the device remains in this mode even if ckref is stopped. to re-enable this mode, the device must be powered down and powered back up with ?logic 0? on ckref. figure 6. serializer timing diagra m using provided bit clock (no ckref) word n-1 word n-1 word n no data no data dp[1:24] dso cks0 cksi strobe b 1 b 2 b 3 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 22 b 23 b 24 b 25 b 26 word n+1 word n serializer operation: (figure 6), diri = 1, no ckref
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 9 deserializer op eration mode the operation of the deserializer is only dependent upon the data received on the dsi data signal pair and the cksi clock signal pair. the following two sections describe the op eration of the deserializer under two distinct serializer source conditions. references to the ckref and strobe signals refer to the signals associated with the serializer device used in generating the serial data and clock signals that are inputs to the deserializer. when operating in this mode, the internal serializer circuitry is disabled, including the parallel data input buffers. if there is a ckref signal provided, the ckso serial clock continues to transmit bit clocks. upon device power-up (s1 or s2 = 1), all deserializer output data pins are driven low until valid data is passed through the deserializer. when the diri signal is asserted low, th e device is configured as a deserializer. data is captured on the serial port and deserialized through use of the bit clock sent with the data. the word boundary is de fined in the actual clock and data sig- nal. parallel data is generated at the time the word boundary is detected. the fall- ing edge of ckp occurs approximately six bit times after the next falling edge of cksi. the rising edge of ckp goes high approximately 13 bit times after ckp goes low. when no embedded word boundary occurs, no pulse is generated on ckp and ckp remains high. figure 7. deserializer ti ming diagram (seria lizer source: ckref equals strobe) the logical operation of the deserializer remains the same if the ckref is equal in frequency to the strobe or at a hi gher frequency than the strobe. the actual serial data stream presented to th e deserializer, however, differs because it has non-valid data bits se nt between words. the duty cycle of ckp varies based on the ratio of the frequency of the ckref signal to the strobe signal. the fre- quency of the ckp signal is equal to the strobe frequency. the falling edge of ckp occurs six bit times after the data transition. the low time of the ckp signal is equal to half (13 bit times) of the ck ref period. the ckp high time is equal to strobe period ? half of the ckref period. figure 8 is representative of a wave- form that could be seen when ckref is not equal to strobe. if ckref is signif- icantly faster, additional non-valid data bits occur between data words. figure 8. deserializer timing diagram (serializer source: ckref does not equal strobe) word n-1 word n+1 word n b 24 b 25 b 26 b 1 b 1 b 2 b 6 b 7 b 8 b 9 b 24 b 19 b 20 b 25 b 26 word n-2 dp[1:24] ckpo cksi dsi word n word n-1 word n-1 word n+1 word n b 24 b j b j+1 b j+13 b j+14 b 25 b 26 b 24 6 bit times 13 bit times b 25 b 26 00 00 word n-2 dp[1:24] ckpo cksi dsi word n word n-1 deserializer operation: diri = 0 (serializer source: ckref = strobe) deserializer operation: diri = 0 (serializer source: ckref does not = strobe)
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 10 embedded word clock operation the fin24c sends and receives serial data source syn- chronously with a bit clock. the bit clock has been modi- fied to create a word boundary at the end of each data word. the word boundary has been implemented by skipping a low clock pulse. this appears in the serial clock stream as three consecutive bit times where signal ckso remains high. to implement this sort of sc heme, two extra data bits are required. during the word b oundary phase, the data tog- gles either high-then-lo w or low-then-high depen- dent upon the last bit of the actual data word. table 2 provides some examples of the actual data word and the data word with the word bou ndary bits added. note that a 24-bit word is extended to 26 bits during serial trans- mission. bit 25 and bit 26 are defined with-respect-to bit 24. bit 25 is always the inverse of bit 24 and bit 26 is always the same as bit 24. this ensures that a ?0? ?1? and a ?1? ?0? transition always occurs during the embedded word phase where ckso is high. the serializer generates the word boundary data bits and the boundary clock condition and embeds them into the serial data stream. the deserializer looks for the end of the word boundary condition to capture and transfer the data to the parallel port. the deserializer only uses the embedded word boundary information to find and capture the data. these boundary bits are stripped prior to the word being sent out the parallel port. lvcmos data i/o the lvcmos input buffers have a nominal threshold value equal to half v ddp . the input buffers are only oper- ational when the device is operating as a serializer. when the device is operating as a deserializer, the inputs are gated off to conserve power. the lvcmos 3-state output buffers are rated for a source/sink current of 2mas at 1.8v. the outputs are active when the diri signal is asserted low. when the diri signal is asserted high, the bi-directional lvcmos i/os are in a high-z state. under purely capacitive load conditions, the output swings between gnd and v ddp . unused lvcmos input buffers must be tied off to either a valid logic low or a valid logic high level to prevent static current draw due to a floating input. unused lvcmos outputs should be left floating. unused bidirectional pins should be connected to gnd through a high-value resistor. if a fin24c devices is configured as an unidirectional serializer, unused data i/o can be treated as unused inputs. if th e fin24c is hardwired as a deserializer, unused date i/o can be treated as unused outputs. figure 9. lvcmos i/o differential i/o circuitry the fin24c employs fsc proprietary ctl i/o technol- ogy. ctl is a low-power, low-emi differential swing i/o technology. the ctl output driver generates a constant output source and sink current. the ctl input receiver senses the current difference and direction from the out- put buffer to which it is connected. this differs from lvds, which uses a constant current source output, but a voltage sense receiver. like lvds, an input source termination resistor is required to properly terminate the transmission line. the fin24c device incorporates an internal termination resistor on the cksi receiver and a gated internal termination resistor on the ds input receiver. the gated terminat ion resistor ensures proper termination regardless of direction of data flow. the rela- tively greater sensitivity of the current sense receiver of ctl allows it to work at much lower current drive and a much lower voltage. during power-down mode, the differential inputs are dis- abled and powered down and the differential outputs are placed in a high-z state. ctl inputs have an inherent fail-safe capability that supports floating inputs. when the cksi input pair of the serializer is unused, it can reli- ably be left floating. altern ately both of the inputs can be connected to ground. ctl inputs should never be con- nected to v dd . when the ckso output of the deserial- izer is unused, it should be allowed to float. from deserializer to serializer from control dp[n] table 2. word boundary data bits 24-bit data words 24-bit data word with word boundary hex binary hex binary ffffffh 1111 1111 1111 1111 1111 1111b 2ffffffh 10 1111 1111 1111 1111 1111 1111b 555555h 0101 0101 0101 0101 01010 0101b 1555555h 01 0101 0101 0101 0101 0101 0101b xxxxxxh 0xxx xxxx xxxx xxxx xxxx xxxxb 1xxxxxxh 01 0xxx xxxx xxxx xxxx xxxx xxxxb xxxxxxh 1xxx xxxx xxxx xxxx xxxx xxxxb 2xxxxxxh 10 1xxx xxxx xxxx xxxx xxxx xxxxb
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 11 figure 10. bi-directional differential i/o circuitry pll circuitry the ckref input signal is used to provide a reference to the pll. the pll generates internal timing signals capa- ble of transferring data at 26 times the incoming ckref signal. the output of the pll is a bit clock sent with the serial data stream. there are two ways to disable the pll: by entering the mode 0 state (s1 = s2 = 0) or upon detecting a low on both the s1 and s2 signals. any of the other modes are entered by asserting either s1 or s2 high and by pro- viding a ckref signal. the pll powers up and goes through a lock sequence. wa it the specified number of clock cycles prior to capturing valid data into the parallel port. when the serdes chipset transitions from a power-down state (s1, s2 = 0, 0) to a powered state (example s1, s2 = 1, 1), ckp on the deserializer transi- tions low for a short duration, then returns high. fol- lowing this, the signal level of the deserializer at ckp corresponds to the seri alizer signal levels. an alternate way of powering down the pll is by stop- ping the ckref signal either high or low. internal cir- cuitry detects the lack of tr ansitions and shuts the pll and serial i/o down. internal references, however, are not disabled, allowing the pll to power-up and re-lock in a lesser number of clock cycles than when exiting mode 0. when a transition is seen on the ckref signal, the pll is reactivated. application mode diagrams mode = 3: unidirectional data transfer figure 11. simplified block diagram for un idirectional serializ er and deserializer figure 11 shows basic operation when a pair of serdes is configured in an unidirectional operation mode. in master operation, the device: 1. is configured as a serializer at power-up based on the value of the diri signal. 2. accepts ckref_m word clock and generate a bit clock with embedded word boundary. this bit clock is sent to the slave devic e through the ckso port. 3. receives parallel data on the rising edge of strobe_m. 4. generates and transmits serialized data on the ds signals source synchronous with ckso. 5. generates an embedded word clock for each strobe signal. in slave operation, the device: 1. is configured as a deserializer at power-up based on the value of the diri signal. 2. accepts an embedded word boundary bit clock on cksi. 3. deserializes the ds data stream using the cksi input clock. 4. writes parallel data onto the dp_s port and generates the ckp_s. ckp_s is only generated when a valid data word occurs. + C + C ds+ ds- gated termination (ds pins only) from serializer to deserializer from control + C + C + C + C ckref_m ckso cksi ckp_s dp[1:20, 23:24]_s serializer control bit ck gen. pll master device operating as a serializer dir = 1 s2 = s1 = 0 slave device operating as a deserializer dir = 0 s2 = s1 = 0 deserializer control work ck gen serializer deserializer register register ds strobe_m dp[1:22]_m
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 12 figure 12. 24-bit unidirectional serializer and deserializer figure 13. unidirectional control, bi-directional data interface flex circuit design guidelines the serial i/o information is transmitted at a high serial rate. care must be taken implementing this serial i/o flex cable. the following best practices should be used when developing the flex cabling or flex pcb: keep all four differential wires the same length. allow no noisy signals over or near differential serial wir es. example: no lvcmos traces over differential wires. use only one ground plane or wire over the differential serial wires. do not run ground over top and bottom. do not place test points on differential serial wires. use differential serial wires a mini mum of 2cm away from the antenna. ckref receiving unit strobe cksi ds dp[1:24] data [0:23] pwrdwn data [0:23] dp[1:24] diri v dd diri s1 s2 s1 s2 ckso ckp ds diro diro fin24c fin24c sending unit refck ckref slave unit strobe cksi ds dp[1:20] dp[21:24] data [0:19] pwrdwn data [0:19] cntl[0:3] dp[1:20] cntl[0:3] dp[21:24] diri diri s1 s2 s1 s2 ckso ckso cksi ckp strobe ds diro diro fin24c fin24c control unit refck
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 13 absolute maximum ratings the ?absolute maximum ratings? are those values beyon d which the safety of t he device cannot be guaranteed. the device should not be operated at t hese limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum ratings . the ?recommended operating conditions? table defines the conditions for actual device operation. recommended operat ing conditions symbol paramete r min. max. unit v dd supply voltage -0.5 +4.6 v all input/output voltage -0.5 +4.6 v lvds output short-circuit duration continuous t stg storage temperature range -65 +150 c t j maximum junction temperature +150 c t l lead temperature (soldering, 4 seconds) +260 c esd rating human body model, 1.5k?, 100pf all pins ckso, cksi, dso to gnd > 2 > 7.5 kv kv symbol paramete r min. max. unit v dda , v dds supply voltage 2.5 2.9 v v ddp supply voltage 1.65 3.6 v t a operating temperature -30 +70 c v dda-pp supply noise voltage 100 mvp-p
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 14 dc electrical characteristics values are provided for over-supply voltage and opera ting temperature ranges, un less otherwise specified. notes: 2. typical values are given for v dd = 2.775v and t a = 25c. positive current values refer to the current flowing into device and negative values means current flowi ng out of pins. voltage is referenced to ground unless otherwise specified (except v od and v od ). 3. v go is the difference in device ground levels between the ctl driver and the ctl receiver. symbol parameter test conditions min. typ. (2) max. unit lvcmos i/o v ih input high voltage 0.65 x v ddp v ddp v v il input low voltage gnd 0.35 x v ddp v v oh output high voltage i oh = ?2.0 ma v ddp = 3.3 0.3 0.75 x v ddp v v ddp = 2.5 0.2 v ddp = 1.8 0.15 v ol output low voltage i ol = 2.0 ma v ddp = 3.3 0.3 0.25 x v ddp v v ddp = 2.5 0.2 v ddp = 1.8 0.15 i in input current v in = 0v to 3.6v ?5.0 5.0 a differential i/o i odh output high source current v os = 1.0v, figure 14 1.75 ma i odl output low sink current v os = 1.0v, figure 14 0.95 ma i oz disabled output leakage current ckso, dso = 0v to v dds , s2 = s1 = 0v 0.1 5.0 a i iz disabled input leakage current cksi, dsi = 0v to v dds , s2 = s1 = 0v 0.1 5.0 a v icm input common mode range v dds = 2.775 5% v go + 0.80 v v go input voltage ground off-set relative to driver (3) see figure 15 0 v r trm cksi internal receiver termination resistor v id = 50mv, v ic = 925mv, diri = 0, | cksi+ ? cksi- | = v id 80.0 100 120 ? r trm dsi internal receiver, termination resistor v id = 50mv, v ic = 925mv, diri = 0, | dsi+ ? dsi- | = v id 80.0 100 120 ?
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 15 power supply currents symbol parameter test condi tions min. typ. max. units i dda1 v dda serializer static supply current all dpi and control inputs at 0v or v ddp , no ckref, s2 = 0, s1 = 1, diri = 1 450 a i dda2 v dda deserializer static supply current all dpi and control inputs at 0 or v ddp , no ckref, s2 = 0, s1 = 1, diri = 1 550 a i dds1 v dds serializer static supply current all dpi and control inputs at 0v or v ddp , no ckref, s2 = 0, s1 = 1, diri = 1 4.0 ma v dds deserializer static supply current all dpi and control inputs at 0v or v ddp , no ckref, s2 = 0, s1 = 1, diri = 0 4.5 i dd_pd v dd power-down supply current i dd_pd = i dda + i dds + i ddp s1 = s2 = 0, all inputs at gnd or v ddp 0.1 a i dd_ser1 26:1 dynamic serializer power supply current i dd_ser1 = i dda + i dds + i ddp ckref = strobe diri = h see figure 16 10mhz 11.0 ma 20mhz 16.0 i dd_des1 1:26 dynamic deserializer power supply current i dd_des1 = i dda + i dds + i ddp ckref = strobe diri = l see figure 16 10mhz 7.5 ma 20mhz 10.0 i dd_ser2 26:1 dynamic serializer power supply current i dd_ser2 = i dda + i dds + i ddp no ckref, strobe active cksi = 15x strobe diri = h, see figure 16 10 mhz 10.0 ma 15 mhz 12.0
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 16 ac electrical characteristics values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. symbol parameter test conditions min. typ. (4) max. units serializer input operating conditions t tcp ckref clock period (10 mhz?20 mhz) see figure 20 50.0 t 100 ns f ref ckref frequency relative to strobe frequency ckref does not equal strobe 1.1 x f st 20.0 mhz t cpwh ckref clock high time 0.2 0.5 t t cpwl ckref clock low time 0.2 0.5 t t clkt lvcmos input transition time see figure 20 90.0 ns t spwh strobe pulse width high/low see figure 20 (t x 4) / 26 (t x 22) / 26 ns f max maximum serial data rate ckref x 26 260 520 mb/s t stc dp (n) setup to strobe diri = 1, see figure 9 (f = 5mhz) 2.5 ns t htc dp (n) hold to strobe 2.0 ns f ref ckref frequency relative to strobe frequency ckref does not equal strobe 1.1 x f strobe 20.0 mhz serializer ac electrical characteristics t tccd transmitter clock input to clock output delay see figure 23, diri = 1, ckref = strobe 33a + 1.5 35a + 6.5 ns t spos ckso position relative to ds see figure 27 (5) ?50.0 250 ps pll ac electrical characteristics t tplls0 serializer pll stabilization time see figure 22 200 s t tplld0 pll disable time loss of clock see figure 27 30.0 s t tplld1 pll power-down time see figure 28 (6) 20.0 ns deserializer input operation conditions t s_ds serial port setup time, ds-to-cksi see figure 25 (7) 1.4 ns t h_ds serial port hold time, ds-to-cks see figure 25 (7) ?250 ps deserializer ac electrical characteristics t rcop deserializer clock output (ckp out) period see figure 21 50.0 t 500 ns t rcol ckp out low time see figure 21 (rising edge strobe) serializer source strobe = ckref where a = (1 / f) / 26 (8) 13a-3 13a+3 ns t rcoh ckp out high time 13a-3 13a+3 ns t pdv data valid to ckp low see fi gure 21 (rising edge strobe) where a = (1 / f) / 26 (8) 8a-6 8a+1 ns t rolh output rise time (20% to 80%) c l = 5pf 2.5 ns t rohl output fall time (80% to 20%) see figure 18 2.5 ns
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 17 notes: 4. typical values are given for v dd = 2.775v and t a = 25c. positive current values refer to the current flowing into device and negative values refer to current flowing out of pins. voltage is referenced to ground unless otherwise specified (except v od and v od ). 5. skew is measured from either the ri sing or falling edge of ckso clock to the rising or falling edge of data (dso). signals are edge aligned. both outputs should have identical load conditions for this test to be valid. 6. the power-down time is a function of the ckref frequ ency prior to ckref being stopped high or low and the state of the s1/s2 mode pins. the specific number of clock cycles required for the pll to be disabled varies based on the operating mode of the device. 7. signals are transmitted from the serializer source synchro nously. in some cases, data is transmitted when the clock remains at a high state. skew should only be measured when data and clock are transitioning at the same time. total measured input skew is a combination of output skew from the serializer, load variations, and isi and jitter effects. 8. rising edge of ckp appears approximatel y 13 bit times after the falling edge of the ckp output. falling edge of ckp occurs approximately eight bit times after a data transition or six bit times after the first falling edge of csko. variation of the data with respect to the ckp signal is due to intern al propagation delay differences of the data and ckp path and propagation delay differences on the various data pins. if the ckref is not equal to strobe for the serializer, the ckp signal does not maintain a 50 % duty cycle. the low time of the ckp remains 13 bit times. control logic timing controls note: 9. deserializer enable time includes the amount of time requi red for internal voltage and current references to stabilize. this time is significantly less than the pll lock time and does not impact overall system startup time. capacitance symbol parameter test conditions min. typ. max. units t phl_dir , t plh_dir propagation delay diri-to-diro diri low-to-high or high-to-low 17.0 ns t plz , t phz propagation delay diri-to-dp diri low-to-high 25.0 ns t pzl , t pzh propagation delay diri-to-dp diri high-to-low 25.0 ns t plz , t phz deserializer disable time: s0 or s1 to dp diri = 0, s1(2) = 0 and s2(1) = low-to-high, figure 30 25.0 ns t pzl , t pzh deserializer enable time: s0 or s1 to dp diri = 0, (10) s1(2) = 0 and s2(1) = low-to-high, figure 30 2.0 s t plz , t phz serializer disable time: s0 or s1 to ckso, ds diri = 1, s1(2) = 0 and s2(1) = high-to-low, figure 28 25.0 ns t pzl , t pzh serializer enable time: s0 or s1 to ckso, ds diri = 1, s1(2) and s2(1) = low-to-high, figure 28 65.0 ns symbol parameter test conditions min. typ. max. units c in capacitance of input only signals, ckref, strobe, s1, s2, diri diri = 1, s1 = s2 = 0, v ddp = 2.5v 2.0 pf c io capacitance of parallel port pins dp[1:12] diri = 1, s1 = s2 = 0, v ddp = 2.5v 2.0 pf c io-diff capacitance of differential i/o si gnals diri = 0, s1 = s2 = 0, v ddp = 2.775v 2.0 pf
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 18 ac loading and waveforms figure 14. differential ctl output dc test circuit figure 15. ctl input common mode test circuit figure 16. ?worst case? serializer test pattern figure 17. ctl output load and transition times figure 18. lvcmos output load and transition times input ds+ ds- r l /2 r l /2 v od v os + C + C dut dut vgo 100 termination + C note: the worst-case test pattern produces a maximum toggling of internal digital circuits, ctl i/o and lvcmos i/o with the pll ope rating at the reference frequency, unless otherwise specified. maximum power is measured at the maximum v dd values. minimum values are measured at the minimum v dd values. typical values are measured at v dd = 2.775v. t 666h 0 b 13 b 14 b 1 b 2 b 6 b 7 b 8 b 11 b 12 b 1 b 2 b 11 b 12 b 1 b 2 b 6 b 7 b 8 11 11 111 00 0 0 0 0 dp[1:12] ckref cks0- cks0+ ds+ ds- 666h 999h t tlh v diff = (ds+) C (ds-) v diff 20% 20% 80% 80% ds+ ds- 5 pf 100 + C t thl t rolh 20% dpn dpn 20% 80% 80% 5pf 1000 t rohl
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 19 ac loading and waveforms (continued) figure 19. serial setup and hold time figure 20. lvcmos clock parameters setup: strobe dp[1:12] strobe t stc t htc data data dp[1:12] setup time hold time mode0 = 0 or 1, mode1 = 1, ser/des = 1 ckref t clkt 90% 90% 10% 10% 50% 50% t clkt v ih v il t tcp t tch t tcl figure 21. deserializer data valid window time and clock output parameters figure 22. serializer pll lock time ckp dp[1:12] t pdv data data valid en_des = 1, cksi, and dsi are valid signals. ckp 50% 75% 50% 25% t rcop t rcoh t rcol setup: cks0 ckref s1 or s2 v dd / v dda t tpls0 note: ckref signal is free running. figure 23. serializer clock propagation delay figure 24. deserializer clock propagation delay strobe cks0- cks0+ t tccd v dd/2 v diff = 0 note: strobe = ckref cksi- cksi+ ckp t rccd v dd/2 v diff = 0
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 20 ac loading and waveforms (continued) figure 25. differential input setup and hold times figure 26. differentia l output signal skew cksi- cksi+ dsi- dsi+ t h_ds t s_ds v diff=0 v diff=0 v id /2 ckso- ckso+ dso- dso+ t sk(p-p) v id / 2 v diff = 0 v diff = 0 note: data is typically edge aligned with the clock. figure 27. pll loss of clock disable time figure 28. pll power-down time cks0 ckref t tppld0 note: ckref signal can be stopped either high or low. cks0 s1 or s2 t tppld1 figure 29. serializer enable an d disable time figure 30. deserializer enable and disable times ds+,cks0+ high-z ds-,cks0- s1 or s2 t plz(hz) t pzl(zh) note: ckref must be active and pll must be stable. s1 or s2 dp t plz(hz) t pzl(zh) note: if s1(2) transitioning, s2(1) must = 0 for test to be valid.
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 21 tape and reel specification dimensions are in millimet ers unless otherwise noted. bga embossed tape dimension note: 10. a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). package a 0 0.1 b 0 0.1 d 0.05 d 1 min. e 0.1 f 0.1 k 0 0.1 p 1 typ. p 0 typ. p 2 0/05 t typ. t c 0.005 w 0.3 w c typ. 3.5 x 4.5 tbd tbd 1.55 1.5 1.75 5. 5 1.1 8.0 4.0 2.0 0.3 0.07 12.0 9.3 tape width dia a max. dim b min. dia c +0.5/?0.2 dia d min. dim n min. dim w1 +2.0/?0 dim w2 max. dim w3 (lsl?usl) 8 330 1.5 13.0 20.2 178 8.4 14.4 7.9 ~ 10.4 12 330 1.5 13.0 20.2 178 12.4 18.4 11.9 ~ 15.4 16 330 1.5 13.0 20.2 178 16.4 22.4 15.9 ~ 19.4 p 1 a 0 d 1 p 0 p 2 f w e d b 0 tc w c k 0 t user direction of feed shipping reel dimension 10 maximum component rotation sketch c (top view) component lateral movement typical component cavity center line 1.0mm maximum w1 measured at hub dia a max dia d min b min dia c dia n see detail aa detail aa w3 w2 max measured at hub 1.0mm maximum typical component center line 10 maximum b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 22 tape and reel specification (continued) dimensions are in millimet ers unless otherwise noted. mlp embossed tape dimension note: 11. ao, bo, and ko dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). package a 0 0.1 b 0 0.1 d 0.05 d 1 min. e 0.1 f 0.1 k 0 0.1 p 1 typ. p 0 typ. p 2 0/05 t typ. t c 0.005 w 0.3 w c typ. 5 x 5 5.35 5.35 1.55 1.5 1.75 5.5 1.4 8 4 2.0 0.3 0.07 12 9.3 6 x 6 6.30 6.30 1.55 1.5 1.75 5.5 1.4 8 4 2.0 0.3 0.07 12 9.3 tape width dia a max. dim b min. dia c +0.5/?0.2 dia d min. dim n min. dim w1 +2.0/?0 dim w2 max. dim w3 (lsl?usl) 8 330 1.5 13 20.2 178 8.4 14.4 7.9 ~ 10.4 12 330 1.5 13 20.2 178 12.4 18.4 11.9 ~ 15.4 16 330 1.5 13 20.2 178 16.4 22.4 15.9 ~ 19.4 p 1 a 0 d 1 p 0 p 2 f w e d b 0 tc w c k 0 t user direction of feed shipping reel dimension 10? maximum component rotation sketch c (top view) component lateral movement typical component cavity center line 1.0mm maximum w1 measured at hub dia a max dia d min b min dia c dia n see detail aa detail aa w3 w2 max measured at hub 1.0mm maximum typical component center line 10 maximum b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 23 physical dimensions dimensions are in millimeter s unless otherwise noted. figure 31. pb-free, 42-ball, ultra small scale ba ll grid array (uss-bga), jedec mo-195, 3.5mm wide bottom view 3.50 4.50 0.5 0.5 3.0 2.5 ?0.30.05 seating plane 0.230.05 0.450.05 (0.75) (0.5) (0.35) (0.6) 0.08 c 0.10 c 0.10 c 0.890.082 1.00 max 0.210.04 (qa control value) 0.10 c c 0.15 c a b 0.05 c x42 terminal a1 corner index area 2x 2x 0.2 +0.1 -0.0 land pattern recommendation
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 24 physical dimensions (continued) dimensions are in millimeter s unless otherwise noted. figure 32. pb-free, 40-terminal, molded leadless package (mlp), quad, jedec mo-220, 6mm square (datum a)
fin24c serdes?low-volta ge 24-bit bi-directiona l serializer/deserializer rev. i20 trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchilds worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms acex? activearray? bottomless? build it now? coolfet? crossvolt ? dome? ecospark? e 2 cmos? ensigna? fact? fast ? fastr? fps? frfet? fact quiet series? globaloptoisolator? gto? hisec? i 2 c? i-lo ? implieddisconnect? intellimax? isoplanar? littlefet? microcoupler? microfet? micropak? microwire? msx? msxpro? ocx? ocxpro? optologic ? optoplanar? pacman? pop? power247? poweredge? powersaver? powertrench ? qfet ? qs? qt optoelectronics? quiet series? rapidconfigure? rapidconnect? serdes? scalarpump? silent switcher ? smart start? spm? stealth? superfet? supersot?-3 supersot?-6 supersot?-8 syncfet? tcm? tinyboost? tinybuck? tinypwm? tinypower? tinylogic ? tinyopto? trutranslation? uhc? unifet? ultrafet ? vcx? wire? across the board. around the world.? the power franchise ? programmable active droop? datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. specifications may change in anymannerwithoutnotice. preliminary first production this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. ?2005 fairchild semiconductor corporation www.fairchildsemi.com fin24c rev. 1.0.2 25

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